Job Name: Analog Design Engineer
Department: ASIC Engineering Group
Responsibilities:
•Develop RF and/or Analog/MS functional blocks and system level IP in CMOS on Cadence / Mentor platforms.
•Responsible for all aspects of development including design, verification and layout.
•Develop and review specifications and verification plans for RF / Analog building blocks.
•Develop and execute testing and characterization plans of the designed blocks.
Experience :
•B.Sc. in Electronic Engineering (M.Sc. is preferable).
•0 – 2 years of RFIC, Analog, or Mixed-Signal design.
•Good knowledge of EDA tools and layout techniques (Cadence or Mentor platforms and Matlab).
•Good system design experience any of the following: transceiver architectures, frequency synthesizers, power management chips or precision analog circuits is a plus.
•Experience in Bluetooth, ZigBee, WiFi or LTE standards transceiver implementation is a plus.
•Working design knowledge in any of the following blocks is highly preferable: RF Front-Ends, Power Amplifiers, PLLsDC-DC converters, ADC’s
•Experience with EM simulations of integrated or PCB passives are a plus.
Candidates are welcome to forward their resumes with an email subject [ADE] to human.resources@si-ware.com
